The present invention relates to a method and/or architecture for generating clocks generally and, more particularly, to a method and/or architecture for generating multiphase high speed clocks.
High bit error rates at high clock rates can limit clock speeds. Conventional clock circuits are implemented having intermediate stages of delay lines or ring oscillators to generate additional clock phases. For example, conventional delay locked loop clock circuits configured to generate four phases include eight serially connected inverter stages and tap every other stage to obtain the four output clock phases. However, conventional clock circuits have one or more of the following deficiencies (i) at high clock rates, the delay through each stage is too great relative to the clock rate and/or (ii) for higher degrees of phase resolution greater numbers of stages are implemented (i.e., to generate 32 phases of a clock, 64 stages are implemented) which can cause even greater delays, excessive chip area, and/or excessive cost.
It would be desirable to have an architecture and/or method for generating multiphase clock signals that may (i) reduce or eliminate latch setup and/or hold errors, (ii) implement programmable phase adjustment, (iii) provide phase adjustment in response to one or more error rates, (iv) be implemented in double data rate applications, and/or (v) be implemented in high clock signal rate applications.
The present invention concerns an apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first phase control signal in response to a phase difference between an input clock signal and an output clock signal. The second circuit may be configured to generate a second phase control signal in response to a phase adjust signal. The third circuit may be configured to generate the output clock signal in response to a phase adjustment of the input clock signal. The phase adjustment may be generated in response to a sum of the first and second phase control signals.
The objects, features and advantages of the present invention include providing a high speed architecture and/or method for generating multiphase clock signals that may (i) implement very accurate clock signal phase offset adjustment, (ii) implement predetermined increments of phase adjustment, (iii) be implemented in double data rate applications, (iv) implement user programmable phase adjustment, (v), implement phase adjustment in response to one or more error rates, (vi) reduce or eliminate latch setup and hold errors, (vii) generate two rising edge and/or two falling edge clock signals, and/or (viii) be implemented in high clock signal rate applications.